Design Check List
          

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SILKSCREEN SPECIFICATIONS

  1. All components on the board require a silkscreen outline.
  2. Reference designators will follow the standard set forth by A.N.S.I. Any designator not listed will be assigned by the customer or Baldwin Tech
  3. All silkscreen lettering will read from left to right, or top to bottom.
  4. All reference designators will be renumbered from left to right, top to bottom, starting with the lowest reference designator number. A back annotation or "was - is" list will be provided to the customer with the finished job. (Not all customers want their PCB’s to be renumbered)
  5. All connectors, edge-fingers, headers, and similar type connection devices will have a "1" silkscreened at pin 1, and the last pin shall have its corresponding pin number silkscreened also.
  6. Polarized capacitors will have a "+" silkscreened outside of their component outline at the positive lead pad.
  7. Socketed components will have a silkscreen outline as shown.
  8. The following PCB Documentation shall appear on the board front silkscreen:
    1. Copyright logo 19XX, Company Name
    2. Board Name
    3. Assembly Number
    4. Assembly Revision Block
    5. Version Block (optional)
    6. Serial Number Block
    7. Made in USA
  9. Any silkscreen which flows over holes which are to be soldered will be eliminated or arranged such that it does not interfere with the soldering of that board

  10. PLCC’s, PQFP’s, or any other high density IC’s shall have their corner pin numbers silkscreened adjacent to the appropriate pad. Large components (over 120 pins) shall have additional hatch marks at every 10th pad. BGA’s and PGA’s shall have their row / column numbers silkscreened along side of them.

 BOARD PHYSICAL SPECIFICATIONS

  1. Boards containing edge-fingers shall have bevel and chamfer notes as shown in figure 1.bevel
  2. Any power or ground traces leading from edge fingers must be of sufficient width to handle the current. (consult with design engineer to provide current requirements)
  3. Conductor width and spacing shall be as wide as possible, but not to the point where it will restrict the router and produce undesirable results. Nominal trace with and spacing shall be 12/12 or 8/8. Trace width & spacing of less than 6/6 will increase board cost and should be reviewed with the customer and evaluated for that specific job.
  4. If micro vias are used in a job, multiple vias must be used to tie the power and ground source into the planes, or to transfer high current traces between layers. Preferably a larger via type should be used for the power application. (the via circumference is calculated by the formula {2 x pi (3.14159) x r})
  5. All trace corners should be made with two 45o angles if possible. 90o corners should be avoided.
  6. If space permits, spare IC locations or prototyping areas should be added to the board on first article products upon customers request.
  7. The following documentation shall appear on the PCB secondary side etched in copper:
    1. Bare board part number
    2. PCB Rev. __
    3. "Secondary Side" or "Solder Side"
  8. The following documentation shall appear on the PCB Primary side etched in copper:
    1. "Primary Side" or "Component Side"
  9. All IC’s, capacitors, diodes, and other components should face the same direction if possible.
  10. Minimum solder mask web shall be 0.005". Nominal solder mask over size shall be 0.010", but may need to be reduced for high density designs.
  11. Observe clearance rules for BGA rework heads or PGA extraction tools.
  12. PCB should have "tented" vias. (covered with solder mask)
  13. Ensure that there are no exposed vias or pads under metal connector shells or other brackets which would short signals together or to ground.
  14. PCB mounting holes shall have an annular ring of the same size or greater than the screw that will secure against it. This will prevent the mounting screw from securing against signal traces.
  15. Mounting holes may or may not be tied to ground. (consult with design engineer and schematic).
  16. All fine pitch I.C.’s shall have fiducials.
  17. Surface mount PCB shall have 3 global fiducials.
  18. PCB shall have 3 non plated 0.125" diameter tooling holes. (auto assembly only)

MISCELLANEOUS SPECIFICATIONS

  1. The following data shall appear on all film layer, just outside the board outline or within a title block:
    1. Company Name
    2. The completion date for film package
    3. Bare board P/N
    4. PCB Revision
    5. Each layers' description and layer number:   EXAMPLE: These layer numbers are based upon a 6 layer board with components on both sides. Actual numbers will vary for boards of a different layer count.
      1. Primary Side Layer 1
      2. Power Plane Layer 2
      3. Internal Trace Layer 3
      4. Internal Trace Layer 4
      5. Ground Plane Layer 5
      6. Secondary Side Layer 6
      7. Silkscreen Primary layer 7
      8. Solder Mask Primary Layer 8
      9. Solder Mask Secondary Layer 9
      10. Silkscreen Secondary Layer 10
      11. SMD Paste Mask Primary Layer 11
      12. SMD Paste Mask Secondary Layer 12
  2. Moiré targets and "crop marks" shall appear on all film layers
  3. Intermediate and final check plots are required for all layers.
  4. 1:1 positive films are required for all board layers.
  5. Assembly Drawing, Fabrication Drawing, and Fab notes are required for all jobs
  6. A back-up disk shall be provided which contains the following data:
    1. PCB Design Data base
    2. PCB Libraries
    3. Gerber Data
      1. Fab Drawing
      2. Fab Notes
    4. Plot / Print files of all film layers, fab and assembly drawings
    5. Schematic Data base
    6. Schematic Libraries
    7. Schematic Plot / Print files

FABRICATION DRAWING NOTES

  • BOARD NAME -
  • BOARD P/N -
  • PCB REVISION -
  • DATE -

NOTES: UNLESS OTHERWISE SPECIFIED

  1. MATERIAL: EPOXY FIBERGLASS FR4 OR EQUIVALENT, _____ +/- 0.007" FINISHED THICKNESS.
  2. FINISHED COPPER THICKNESS TO BE ___ oz. EXTERNAL LAYERS, ___ oz. INTERNAL LAYERS (MULTI-LAYERED BOARDS)
  3. MINIMUM COPPER PLATING .001 THICK FOR PLATED THROUGH HOLES. ANNULAR RING TO BE 0.002 MINIMUM.
  4. SOLDER MASK OVER BARE COPPER, BOTH SIDES, GREEN IN COLOR. (.002" MAX THICKNESS FOR SMD BOARDS)
  5. SOLDER MASK REGISTRATION +/- 0.003". ALL TRACES ADJACENT TO PADS SHALL BE COMPLETELY COATED WITH SOLDER MASK.
  6. ALL EXPOSED COPPER AREAS TO BE SOLDER COATED.
  7. SILKSCREEN _________ SIDE(S) USING WHITE EPOXY INK.
  8. HOLE DIAMETER TOLERANCE IS +/- 0.003" AFTER PLATING
  9. HOLE LOCATION +/- 0.003". MAXIMUM LAYER TO LAYER MISREGISTRATION SHALL BE 0.005". MEASUREMENT METHOD MUST COMPLY TO MIL-P-55110D, FIGURE 1.
  10. FINISHED CONDUCTOR WIDTH SHALL NOT VARY MORE THAN +/- 10% FROM ARTWORK MASTER.
  11. WARP AND TWIST OF BOARD SHALL NOT EXCEED 0.010" INCH PER INCH.
  12. ALL DIMENSIONS ARE IN INCHES. TOLERANCES: .XX = +/- 0.010", .XXX = +/- 0.005".
  13. ACCEPTABILITY REQUIREMENTS PER IPC-A-600E.
  14. VENDORS UL APPROVED LOGO TO BE LOCATED ON SOLDER SIDE OF BOARD.
  15. DRAWING IS VIEWED FROM COMPONENT OR PRIMARY SIDE.
  16. THIS IS A _ LAYER BOARD.
  17. ALL HOLES ARE PLATED THROUGH EXCEPT SIZE ___, QTY.= __.
  18. GOLD PLATE FINGERS 0.000030" THICK GOLD OVER 0.000100" NICKEL.
  19. DRILL SIZE UNITS ARE THOUSANDTHS OF AN INCH.
  20. DO NOT TRIM SILKSCREEN WHICH FLOWS OVER VIA HOLES.
  21. RADIUS INTERNAL / EXTERNAL SHARP CORNERS 0.062R (XX PL.)

 

Baldwin Technologies
1736 S. Nevada Way  Suite B
Mesa, Arizona 85204
Phone 480-539-4400    Fax 480-539-4500